1. Field of the Invention
The present invention relates to phase-locked loop (“PLL”) circuits, and, more particularly, to a loop filter for a PLL circuit. More specifically, the present invention relates to a low-noise loop filter for a PLL circuit.
2. Description of Related Art
A phase-locked loop (“PLL”) circuit generally includes a phase detector, a loop filter, and a controlled oscillator. The phase detector receives an input signal, which has a reference frequency. The output signal of the controlled oscillator is fed back to the phase detector. The frequency of the output signal is typically a multiple of the reference frequency of the input signal. The PLL circuit is utilized to lock the output frequency to the input frequency. Locking the output frequency to the input reference frequency is critical in various applications, such as developing accurate and precise clocks for digital signal processors (“DSPs”) and for audio sampling frequencies and rates. Fast locking applications also exist in which adaptive bandwidth PLLs have been developed and used.
PLL circuits in mixed-signal integrated circuit designs typically operate in noisy environments. Much of the noise is introduced through the current or voltage supplies, the substrate, temperature variations, process parameters, or other such sources. Low jitter PLL circuits require high loop bandwidths to reject the noise.
Passive loop filters for PLL circuit designs are popular due to their simplicity, but the control of their loop time constants lacks flexibility. Active loop filters used in conjunction with feed-forward charge pumps provide a wider range of loop time constants and often provide a decreased area of on-chip capacitance. Fully differential charge pumps for PLL circuit designs have been of great interest due to their ability to reject noise. However, fully differential charge pumps require increased on-chip capacitance and extra circuitry for common mode feedback. One drawback of a charge pump PLL circuit is that setting the loop filter pole position requires a compromise between the loop phase margin and the jitter performance.
Typical charge pump PLL circuits having two poles at the origin require a zero to be introduced in the loop for stability. A common method of adding a zero is to couple a resistor in series with the charge pump capacitor. FIG. 1A shows a loop filter 100A according to the prior art in which a resistor is coupled in series with a charge pump capacitor to provide stability. Loop filter 100A includes a charge pump (CP) 101 with a current output, a charge pump capacitor 102, and a resistor 104. CP 101 is coupled to charge pump capacitor 102, and charge pump capacitor 102 is, in turn, coupled to resistor 104. Resistor 104 is further coupled to ground.
Another common method of adding a zero is to use an op-amp virtual ground technique. FIG. 1B shows another loop filter 100B according to the prior art. Loop filter 100B has a charge pump 105, a capacitor 106, an amplifier 107, a resistor 108, a filtering resistor 110, and a filtering capacitor 112. Capacitor 106 and resistor 108 are coupled together in series and along a feed-back path of amplifier 107. Filtering resistor 110 and filtering capacitor 112 are coupled in series between amplifier 107 and ground and further filter the output from amplifier 107. This higher-frequency pole is commonly added to improve the loop noise characteristics at some expense to loop stability.
Most charge pump PLLs use a proportional signal that is based on the instantaneous time difference. The signal in lock is characterized by narrow high amplitude pulses, that even after filtering, lead to an abrupt variation of the oscillator control signal and rapid frequency changes that degrade the jitter performance of the PLL circuit. Typical charge pump loop filters each involves a small period of time in which most of the loop filtering actions, such as transients, charge sharing, charge injection, etc., occurs. Additionally, the output of a charge pump loop filter is generally a sum of the integral of the phase error or difference and a proportionate term. The charge pump loop filter typically has another one-pole filter that helps remove high frequency “noise”, but the addition of this other one-pole filter negatively affects the phase response of the closed loop.
A solution to this “other one-pole filter” problem has been proposed in U.S. patent application Ser. No. 10/043,558 filed on Jan. 10, 2002 which has issued as U.S. Pat. No. 6,690,240 on Feb. 10, 2004, and in U.S. continuation patent application Ser. No. 10/612,200 filed on Jul. 3, 2003. which issued as U.S. Pat. No. 6,825,864 filed on Dec. 7, 2004, which both are entitled “LOW-JITTER LOOP FILTER FOR A PHASE-LOCKED LOOP SYSTEM” by Adrian Maxim, Baker Scott III, Edmund M. Schneider, and Melvin L. Hagge (hereafter “the Maxim reference”). The solution in the Maxim reference generally proposes separating the proportionate terms from the integral terms within the loop filter. By separating the proportionate and integral terms, some optimizations for the PLL circuit are able to be achieved.
With reference now to FIG. 2, an exemplary phase-locked loop (“PLL”) circuit 200 according to the Maxim reference is shown. PLL circuit 200 includes a phase frequency comparator (“PFC”) 204, a loop filter system 205 that includes a current adder (“Σ”) 214, and a current controlled oscillator (“ICO”) 216 coupled together in series. An N divider 202 is coupled to a positive input node of PFC 204. An M divider 218 is coupled to the output of ICO 216, and the output of M divider 218 is coupled and fed back to a negative input node of PFC 204. An input signal 201 is fed into N divider 202 and divides input signal 201 by a factor of N to provide input reference signal 203. The N-divided input reference signal 203 is fed as an input signal into PFC 204. Furthermore, an output signal 220 of PLL circuit 200 is fed into an M divider 218 as shown in FIG. 2. M divider 218 divides output signal 220 by a factor of M to provide an input feedback signal 219. The M-divided input feedback signal 219 is fed back as an input signal into the negative input node of PFC 204.
Loop filter system 205 has a separate proportional signal path 207 and a separate integral signal path 211. Proportional signal path 207 includes a charge pump (“CP”) 206 coupled in series with a loop filter device (“filter”) 208. The output of PFC 204 is coupled to the input of CP 206, and the output of CP 206 is coupled to the input of filter 208. The output of filter 208 is then fed into current adder 214. Integral signal path 211 has another charge pump (“CP”) 210 coupled in series with another loop filter device (“LPF”) 212. The output of PFC 204 is coupled to the input of CP 210, and the output of CP 210 is coupled to the input of LPF 212. The output of LPF 212, in turn, is fed into current adder 214.
However, the component structures and operations of proportional path 207 and integral path 211 can be fairly complex and involved. For example, proportional path 207 and integral path 211 each utilizes its own respective CP 206 and 210. Furthermore, filter 208 of proportional path 207 can include a transconductance stage, various capacitors, and a series of hold and reset switches for the capacitors and charge pumps. LPF 212 of integral path 211 can include a loop filter stage having a capacitor, a transistor, and a resistor. The complexity of proportional path 207 and integral path 211 places certain circuit constraints on the loop filter and PLL circuit and can contribute to poor transient behavior by the loop filter.
The present invention recognizes the desire and need for further reducing the noise and jitter in a PLL circuit. The present invention further recognizes the desire and need to simplify the components for the proportional path and integral path of a loop filter for a PLL circuit. The present invention also recognizes the desire and need to relieve circuit constraints and improve transient behavior for a loop filter of a PLL circuit. The present invention overcomes the problems and disadvantages in accordance with the prior art.